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IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
FEATURES:
* * * * * *
IDTQS74FCT2823AT/BT
DESCRIPTION:
CMOS power levels: <7.5mW static Undershoot clamp diodes on all outputs True TTL input and output compatibility Ground bounce controlled outputs Reduced output swing of 0 to 3.5V Built-in 25 series resistor outputs reduce reflection and other system noise * A and B speed grades * IOL = 12mA * Available in SOIC and QSOP packages
The IDTQS74FCT2823T is a 9-bit high-speed CMOS TTL-compatible buffered register with 3-state outputs, with a 25 resister that is useful for driving transmission lines and reducing system noise. The 2823 series parts can replace the 823 series to reduce noise in an existing design. All inputs have clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression. Outputs will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
EN
14
D Dx CP
13
Q 25 CP CLR
Yx
CLR OE
11 1
INDUSTRIAL TEMPERATURE RANGE
1
c 2002 Integrated Device Technology, Inc.
MARCH 2002
DSC-5257/4
IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG IOUT IIK IOK Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max Sink Current/Pin Input Diode Current, VIN < 0 Output Diode Current, VOUT < 0 Max -0.5 to +7 -65 to +150 120 -20 -50 Unit V C mA mA mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN CIN
(2) (3)
Parameter(1) Input Capacitance Input Capacitance Output Capacitance Output Capacitance
Conditions VIN = 0V VIN = 0V VOUT = 0V VOUT = 0V
Typ. 4 8 6 8
Max. -- -- -- --
Unit pF pF pF pF
COUT(4)
SOIC/ QSOP TOP VIEW
COUT(5)
NOTES: 1. This parameter is measured at characterization but not tested. 2. Pins 1, 3-11, 13. 3. Pin 2. 4. Pins 15-22. 5. Pins 14, 23.
PIN DESCRIPTION LOGIC SYMBOL
9 9
Pin Names Dx CLR I/O I I Description D Flip-Flop Data Inputs When the clear input is LOW and OE is LOW, the Yx outputs are LOW. When clear input is HIGH, data can be entered into the register. Clock Pulse for the register. Enters data into the register on the LOW-to-HIGH transition. Register 3-State Outputs Clock Enable. When the clock enable is LOW, data on the Dx input is transferred to the Yx output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the Yx outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Yx outputs are in the high impedance state. When the OE input is LOW, the TRUE register data is present at the Yx outputs.
Dx
D CP EN
Q CLR
Yx
CP Yx EN
I O I
CP EN CLR OE
OE
I
2
IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
Inputs OE H H H L H L H H L L
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care NC = No Change = LOW-to-HIGH transition Z = High-Impedance
Internal Dx L H X X X X L H L H CP X X X X Qx L H L L NC NC L H L H
Outputs Yx Z Z Z L Z NC Z Z L H Function High Z High Z Clear Clear Hold Hold Load Load Load Load
CLR X X L L H H H H H H
EN L L X X H H L L L L
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol VIH VIL VT IIH IIL IOZ IOR VIC VOH VOL ROUT(3) Parameter Input HIGH Level Input LOW Level Input Hysteresis Input HIGH Current Input LOW Current Off-State Output Current (Hi-Z) Current Drive Input Clamp Voltage Output HIGH Voltage Output LOW Voltage Output Resistance VCC = Max 2.0V(2) 0 VIN VCC -- 50 -- 2.4 -- 18 -- -- -0.7 -- -- 25 5 -- -1.2 -- 0.5 40 A mA V V V VCC = Max., VOUT = VCC = Min, IIN = -18mA , TA = 25C(2) VCC = Min. VCC = Min. VCC = Min. IOH = -15mA IOL = 12mA IOH = 12mA Test Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VTLH - VTHL for all inputs VCC = Max. 0 VIN VCC Min. 2 -- -- -- Typ.(1) -- -- 0.2 -- Max. -- 0.8 -- 5 Unit V V V A
NOTES: 1. Typical values are at VCC = 5.0V, TA = 25C. 2. This parameter is measured at characterization but not tested. 3. ROUT changed on March 8, 2002. See rear page for more information.
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IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol ICC Parameter Quiescent Power Supply Current
ICC
Supply Current per Input TTL Inputs HIGH
ICCD
Supply Current per Input per MHz
Test Conditions(1) VCC = Max. freq = 0 0V VIN 0.2V or VCC - 0.2V VIN Vcc VCC = Max. VIN = 3.4V(2) freq = 0 VCC = Max. Outputs Open and Enabled One Bit Toggling 50% Duty Cycle Other inputs at GND or Vcc(3,4)
Min. --
Max. 1.5
Unit mA
--
2
mA
--
0.25
mA/MHz
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TLL driven input (VIN = 3.4V). 3. For flip-flops, ICCD is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption only and does not include power to drive load capacitance or tester capacitance. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol tPLH tPHL tPLH tPHL tSU tH tENS tENH Parameter Clock to Y Delay OE = LOW Clock to Y Delay OE = LOW(2) Data to CP Setup Time Data to CP Hold Time EN to CP Setup Time EN to CP Hold Time FCT2823AT Min. Max. -- 10 -- 4 2 4 2 20 -- -- -- -- FCT2823BT Min. Max. -- 7.5 -- 3 1.5 3 0 15 -- -- -- -- Unit ns ns ns ns ns ns
NOTES: 1. CLOAD = 50pF, RLOAD = 500 unless otherwise noted. 2. CLOAD = 300pF.
TIMING REQUIREMENTS OVER OPERATING RANGE(1)
Symbol tCLR tREC tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Parameter(2) CLR to Y Delay CLR to CP Setup Time Clock Pulse Width HIGH or LOW Output Enable Time OE to Yx Output Enable Time(3) OE to Yx Output Disable Time(4) OE to Yx Output Disable Time OE to Yx FCT2823AT Min. Max. -- 11 6 -- 7 -- -- -- -- -- 12 23 7 9 FCT2823BT Min. Max. -- 9 6 -- 6 -- -- -- -- -- 8 -- 6.5 7.5 Unit ns ns ns ns ns ns ns
NOTES: 1. CLOAD = 50pF, RLOAD = 500 unless otherwise noted. 2. See Test Circuits and Waveforms 3. CLOAD = 300pF. 4. CLOAD = 5pF.
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IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
VCC 500 Pulse Generator VIN D.U.T. 50pF RT CL 500 VOUT
7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
FCTL link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
FCTL link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
FCTL link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
FCTL link
DISABLE 3V 1.5V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ
0V 3.5V 0.3V VOL VOH 0V
FCTL link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDTQS74FCT2823AT/BT HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDTQS XX FCT XXXX Device Type Temp. Range XX Package
SO Q
Small Outline IC (gull wing) Quarter Size Small Outline Package
2823AT High-Speed CMOS Bus Interface 9-Bit Register 2823BT 74 -40C to +85C
As per PCN L0201-02, the Output Resistance (ROUT) specifications have changed as of March 8, 2002. The original specifications were:
Parameter ROUT Description VCC = Min, IOL = 12mA Min. 20 Typ. 28 Max. 40 Unit
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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